AMD Doubled FPUs on AMD Jaguar Computing Core

Fabless CPU and GPU designer, Texas-based American company Advanced Micro Devices is working very hard to deliver a new low-power successor to the famous Bobcat computing architecture. The new microprocessor design is called Jaguar and, during this year’s Hot Chips conference, interesting architectural developments were revealed, like we reported here.

Bobcat was AMD’s first microprocessor architecture specifically designed for low-power usage models, as this is the way the company attempts to improve one of its historical weak points. While the Texan company has managed several times during its existence to release desktop and server processors that manifested supreme performance, AMD was never able to conquer the mobile market. Since Intel decided to make so much fuss about low-performance CPUs that were deemed desirable because they had a drastically low power consumption, AMD designed Bobcat as a direct competitor for this market sector. Compared with Intel’s current Atom, AMD’s Bobcat is completely superior when computing performance is the main concern. It is dramatically superior if 3D graphics performance is the main criteria and has admirable low power requirements despite using an older and larger manufacturing node.

Many were eagerly expecting the new Jaguar design, as this was considered to be almost revolutionary because AMD even skipped one generation that was the initial successor to Bobcat and went directly for Jaguar. We wouldn’t call it revolutionary, but the new low-power design is considerably different from Bobcat and there’s no better place to observe this than in the floating point computing units. AMD has added a lot of new SIMD capabilities and lots of new instruction sets to its new design and an overhaul of the floating point unit (FPU) was clearly needed. Jaguar now comes with most – if not all – of Bobcat’s abilities, but it also adds complete architectural computational support for SSE4.1, SSE4.2, AES, CLMUL, MOVBE, AVX, XSAVE, XSAVEOPT, FC16, and BMI instructions.

Since most SIMD instructions are 128-bit wide – if not wider, AMD decided to double the width of its FPU pipelines from 64-bit to 128-bit. SSE instructions required two passes on the Bobcat, but they now can be handled in one single pass, and this is no small feat. Ironically for AMD, Jaguar comes with support for AVX and these would be best fit by 256-bit wide FPU pipelines, but this is not the main concern for a mobile-oriented architecture. There isn’t much software that uses the AVX code base right now and, while we’re sure AVX will become increasingly important in the future, AMD will probably have better AVX capabilities when the set becomes an absolute necessity. Therefore, Jaguar comes with lot of new instructions and greatly improved FPU units that will make your multimedia applications and games fly.

AMD Marketing Shot
Image credits to AMD

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