AMD Jaguar Comes with AVX, BMI, SSE 4.2, AES Instructions

Famous Texas-based fabless CPU designer, Advanced Micro Devices, is now working hard to finalize its Jaguar project. The AMD Jaguar is the company’s successor to the very successful low-power Bobcat architecture found inside today’s Brazos and Brazos 2.0 platforms.

Unlike AMD’s Piledriver, the Jaguar micro-architecture will be a radical evolution from today’s Bobcat. The Piledriver architecture is regarded as an evolutionary step of Bulldozer and many think of it as what Bulldozer should have been in the first place. The low-power Bobcat architecture was a complete success, and the latest numbers showed AMD is ruling over 43% of the desktop PC market. Bobcat was targeted against Intel’s Atom, and the first-generation low-power architecture from AMD proved superior in absolutely every aspect. While Bobcat was perfectly fitted for low-power desktops, nettops, netbooks and bigger tablets, the company lacked tablet solution, and tablets are obviously the next big thing.

The importance of tablets in the computer market is tremendous. There are about 348 million PCs shipping this year all over the world, and the numbers will reportedly double in the next half decade. However, in five years tablet sales will actually reach higher numbers than the entire desktop PC market of 2012. Therefore, it makes perfect sense for AMD to have a powerful low-power micro-architecture to address this market and others. Jaguar will be quite different from Bobcat, as it will likely have a unified 2MB cache and will probably use AMD’s second-generation GCN architecture, like we reported here. The x86 computing cores will be seriously modified. The IPC will be increased and the company will reportedly add support for BMI and TBM instructions.

AMD defines these instructions as: 

“The BMI and TBM instruction sets allow common bit manipulation operations to be executed in fewer instructions. This can save cycles, reduce code size, and reduce usage of temporary registers.” Jaguar will also bring AVX instruction support just like AMD’s Bulldozer and Intel’s Sandy Bridge. These instructions were first proposed back in 2008 and allow a three-opera scenario where SIMD instructions are involved. These are a high performance instruction sets used by powerful processors like Intel’s Ivy Bridge and AMD’s Bulldozer, and it’s quite surprising to see AMD implementing this in a low-power architecture.

Only Intel’s Haswell will have something superior, namely AVX2. AMD’s Jaguar will likely bring support for SSE4.1, SSE4.2, AES, PCLMUL, AVX, BMI, F16C instructions as well as MOVBE. The company will also hold a technological manufacturing advantage in the fact that the Kabini and Temash processors are going to be manufactured in 28nm technology, while Intel’s next-generation Atom will still be made in 32nm.

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Image credits to AMD

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