AMD Trinity Architectural Preview - Part III

As we’ve said in the beginning, SOI helps reducing leakage, power consumption and increases the achievable frequency.This is exactly why Trinity is able to achieve such low power consumption levels like 15W / 25W and 35W.

The Trinity APU will have working frequencies between 2 GHz and 3.8 GHz.

Other than refining the design, what else would make Trinity achieve such high clock frequencies when compared to Llano that’s made using the same process?

The answer is in the technology AMD licensed from Cyclos Semiconductor.

Trinity is specially designed to include and use Cyclos’ “clock mesh” technology, which supposedly delivers significant power savings.

Microprocessors rely on a clock rate, which must be propagated across the surface of the chip.

This controls the functioning of the entire chip and thus, the clock signal must avoid inconsistency.

There can be clock signal jitter (variances between two clock pulses) and skew (pulses that arrive at different areas of the chip at different times). 

When running a chip at 4 GHz, that CPU’s clock switches 4 billion times a second. Any inconsistency will be amplified 4 billion times and the CPU would practically be defective.

High-end microprocessors have a clock mesh. This minimizes skew, but uses significantly more power than a clock tree. There are various estimates about how much a clocking design will affect the CPU’s overall power consumption.

The bottom line is that Cyclos themselves are claiming that using their technology can cut total IC power by up to 10%.

Cyclos' design contains a tank circuit (also known as an LC circuit) that stores energy. Electricity will pass from the capacitor to the inductor and a magnetic field will manifest.

When the capacitor will reach the zero charge level, the flow of current will be reversed and the magnetic field will dissipate.

This process is similar to the movement of a pendulum or the ticking of the clock. It has also been compared to the sloshing of water in a tank, which is where the “tank circuit” concept coming from.

This kind of clock generation will reduce the "clocking" power consumption “up to 24% while maintaining the low clock-skew target required by high-performance processors,” according to Cyclos.

The power reduction obtained by changing the clock generation method, is estimated as representing around 10 percent of the chip’s total power consumption.

AMD seems to have refined their APU design and, along with this new clock mesh and other design improvements, managed to get the maximum clock speed from 2900 Mhz in Llano’s case to 3800 MHz on Trinity.

This is a considerable 31% frequency improvement despite the fact that they are using the same 32 nm SOI process.

Strangely, Trinity has a bigger die size of 246 square millimeters. That’s bigger than Llano’s 228 square millimeters despite the fact that Llano comes with 1.45 billion transistors versus Trinity’s 1.303 billion.

This clearly shows that the Trinity design is likely better distributed and more efficient. And by well distributed we mean that AMD might have done some rearranging of the CPU’s hot units so that they don create hot spots that will harm the CPU’s ability to achieve high frequencies.

The different number of transistors may also come from the fact that some functions are different. As we’ve said before, FMA support changed from FMA4 to FMA3 and the Bulldozer cores were replaced with more efficient and better performing Piledriver cores.

We should also consider that Trinity has a different UVD engine and that those 384 Stream Processing Units are using the VLIW4 design from the Radeon HD 6000 series rather than the VLIW5 cores that Llano got from the old Radeon HD 5570.

Remember that AMD’s Radeon 6870 had around half a billion less transistors when compared to the VLIW5 based Radeon HD 5870. 

Despite having 25% less transistors, the Radeon 6870 was able to be roughly equal to the Radeon HD 5870 or even surpass it in some situations.

Even if Cypress (HD5870) was able to beat Barts (HD 6870) some tests, Barts was never more than 10% behind. To build a 25% smaller design and only loose 10% of the performance in some cases , but win in other cases, is going for a more efficient solution.

The same move for a more efficient solution with more performance despite fewer transistors we can see in AMD Trinity and its integrated graphics processing unit (iGPU).

AMD’s Llano and Brazos were very successful. They’ve represented the fastest microprocessor ramp in the company’s history and now AMD rules 43% of the desktop CPU market despite the fact that they don’t have a high end solution at any price point.

AMD now needs volume and, with Trinity, they’ll need even more volume as Trinity will only increase AMD’s Fusion success.

So choosing the right manufacturing process and the right foundry becomes a serious problem for AMD and, because the sales are so good, AMD can’t develop a design and then search for a foundry to manufacture it. They must do exactly the other way around.

AMD must have a design compatible with more then one FAB. If the Texas based CPU manufacturer wants to compete with Intel’s volumes, they can’t work only with the Dresden FAB.

But more about AMD’s new Trinity APU, about manufacturing foundries and choosing the right design in Part IV of our AMD Trinity Architectural Preview.

Posted in: Hardware, Preview